1. Technical Field
The present disclosure relates to computer systems and digital signal processors (DSP), and more particularly, to multi-processor systems.
2. Description of the Related Art
The present application relates to electronic systems, especially digital electronic systems such as computers, digital signal processors (DSP), and these systems embedded in larger systems. More particularly the concept relates to signal networks within digital electronic systems, and especially to synchronization signal networks within multi-processor arrays (MPAs). An MPA is composed of a group of processing elements (PE), supporting memories (SM), and a primary interconnection network (PIN) that supports high bandwidth data communication among the PEs and memories.
A PE has registers to buffer input data and output data, an instruction processing unit (IPU), and logic/circuitry for performing arithmetic and logic functions on the data plus a number of switches and ports to communicate with other parts of the system. The IPU fetches instructions from memory, decodes them, and sets appropriate control signals to move data in and out of the processor and to perform arithmetic and logical functions.
Memory for computers and DSP is organized in a hierarchy with fast memory at the top and slower but higher capacity memory at each step down the hierarchy. In an MPA, supporting memories at the top of the hierarchy are located adjacent to each PE. Each supporting memory may be specialized to hold only instructions or only data. Supporting memory for a particular PE may be private to that PE or shared with other PE.
MPAs were first constructed as arrays of digital integrated circuits (ICs) on circuit boards, each IC containing one processor, and the circuit board providing the data communication links to interconnect the processors. The continuing progress in very large scale integration (VLSI) technology based on complementary metal oxide silicon (CMOS) transistor circuits with finer fabrication dimensions has resulted in great increases in the densities of logic and memory circuits per silicon IC chip. Today, on a single IC chip, MPAs are made with a hundred or more processors and their supporting memories and interconnection networks. These MPA chips may be further interconnected on circuit boards to make larger systems.
PEs suitable for MPA may be more energy efficient than general purpose processors (GPP), simply because of the large number of PEs per MPA chip, and the extra energy becomes extra waste heat and its removal adds to chip packaging and operational costs.